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| M24164 16 Kbit Serial I2C BUS EEPROM PRELIMINARY DATA TWO WIRE I2C SERIAL INTERFACE SUPPORTS 400kHz PROTOCOL 1 MILLION ERASE/WRITE CYCLES 40 YEARS DATA RETENTION 2ms TYPICAL PROGRAMMING TIME SINGLE SUPPLY VOLTAGE: - 4.5V to 5.5V for M24164 - 2.5V to 5.5V for M24164-W - 1.8V to 5.5V for M24164-R HARDWARE WRITE CONTROL BYTE and PAGE WRITE (up to 16 BYTES) BYTE, RANDOM and SEQUENTIAL READ MODES SELF TIMED PROGRAMMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD/LATCH-UP PERFORMANCES DESCRIPTION The M24164 is a 16 Kbit EEPROM. The memory is an electrically erasable programmable memory (EEPROM) fabricated with STMicroelectronics's High Endurance Single Polysilicon CMOS technology which guarantees an endurance typically well above one million erase/write cycles with a data retention of 40 years. The "-W" version operate with a power supply value as low as 2.5V and the "-R" version operate down to 1.8V. Both Plastic Dual-in-Line and Plastic Small Outline packages are available. Table 1. Signal Names E0-E2 SDA SCL WC VCC VSS January 1999 Chip Enable Inputs Serial Data Address Input/Output Serial Clock Write Control Supply Voltage Ground 8 1 PSDIP8 (BN) 0.25mm Frame 8 1 SO8 (MN) 150mil Width Figure 1. Logic Diagram VCC 3 E0-E2 SCL WC M24164 SDA VSS AI02264 1/16 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. M24164 Table 2. Absolute Maximum Ratings (1) Symbol TA TSTG TLEAD VIO VCC VESD Parameter Ambient OperatingTemperature Storage Temperature Lead Temperature, Soldering Input or Output Voltages Supply Voltage Electrostatic Discharge Voltage (Human Body model) Electrostatic Discharge Voltage (Machine model) (4) (3) (2) Value -40 to 125 -65 to 150 Unit C C C V V V V (PSDIP8 package) (SO8 package) 10 sec 40 sec 260 215 -0.6 to 6.5 -0.3 to 6.5 4000 500 Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Depends on range. 3. MIL-STD-883C, 3015.7 (100pF, 1500 ). 4. EIAJ IC-121 (Condition C) (200pF, 0 ). Figure 2A. DIP Pin Connections Figure 2B. SO Pin Connections M24164 E0 E1 E2 VSS 1 2 3 4 8 7 6 5 AI02265 M24164 VCC WC SCL SDA E0 E1 E2 VSS 1 2 3 4 8 7 6 5 AI02266 VCC WC SCL SDA DESCRIPTION (cont'd) The memory is compatible with the two wire serial interface which uses a bi-directional data bus and serial clock. The memory offers 3 chip enable inputs (E2, E1, E0) so that up to 8 x 16K devices may be attached to the bus and selected individually. The memory behaves as a slave device with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition generated by the bus master. The START condition is followed by a stream of 7 bits, plus one read/write bit and terminated by an acknowledge bit (see Table 3). When writing data to the memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition. Power On Reset: VCC lock out write protect. In order to prevent any possible data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is implemented. Until the VCC voltage has reached the POR threshold value, the internal reset is active, all operations are disabled and the device will not respond to any command. In the same way, when VCC drops down from the operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable VCC must be applied before applying any logic signal. 2/16 M24164 Table 3. Device Select Code Chip Enable Bit Device Select Note: The MSB b7 is sent first. MSB Address b4 E0 b3 A10 b2 A9 b1 A8 RW b0 RW b7 1 b6 E2 b5 E1 Table 4. Operating Modes (1) Mode Current Address Read Random Address Read Sequential Read Byte Write Page Write Note: 1. X = VIH or VIL. RW bit '1' '0' '1' '1' '0' '0' WP X X X X VIL VIL Data Bytes 1 1 1 1 16 Initial Sequence START, Device Select, RW = '1' START, Device Select, RW = '0', Address, reSTART, Device Select, RW = '1' As CURRENT or RANDOM Mode START, Device Select, RW = '0' START, Device Select, RW = '0' SIGNAL DESCRIPTIONS Serial Clock (SCL). The SCL input pin is used to synchronize all data in and out of the memory. A resistor can be connected from the SCL line to VCC to act as a pull up (see Figure 3). Serial Data (SDA). The SDA pin is bi-directional and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A resistor must be connected from the SDA bus line to VCC to act as pull up (see Figure 3). Chip Enable (E2 - E0). These chip enable inputs are used to set 3 bits (b6, b5, b4) of the 7 bit device select code. These inputs may be driven dynamically or tied to VCC or VSS to establish the device select code. Write Control (WC). A hardware Write Control pin (WC) is provided on pin 7 of the memory. This feature is useful to protect the entire contents of the memory from any erroneous erase/write cycle. The Write Control signal is used to enable (WC=VIL) or disable (WC=VIH) write instructions to the entire memory area. When unconnected, the WC input is internally read as VIL and write operations are allowed. When WC=1, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged. Refer to Application Note AN404 for more detailed information about Write Control feature. DEVICE OPERATION I2C Bus Background The memory supports the I2C protocol. This protocol defines any device that sends data onto the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master will always initiate a data transfer and will provide the serial clock for synchronisation. The memory is always a slave device in all communications. Start Condition. START is identified by a high to low transition of the SDA line while the clock SCL is stable in the high state. A START condition must precede any command for data transfer. Except during a programming cycle, the memory continuously monitors the SDA and SCL signals for a START condition and will not respond unless one is given. Stop Condition. STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the memory and the bus master. A STOP condition at the end of a Read sequence, after and only after a No-Acknowledge, forces the standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle. 3/16 M24164 Acknowledge Bit (ACK). An acknowledge signal is used to indicate a successful data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse period the receiver pulls the SDA bus low to acknowledge the receipt of the 8 bits of data. Data Input. During data input the memory samples the SDA bus signal on the rising edge of the clock SCL. Note that for correct device operation, the SDA signal must be stable during the clock low to high transition and the data must change ONLY when the SCL line is low. Memory Addressing. To start communication between the bus master and the slave memory, the master must initiate a START condition. Following this, the master sends onto the SDA bus line 8 bits (MSB first) corresponding to the Device Select code (7 bits) and a READ or WRITE bit. Three out of the four most significant bits of the Device Select code are the Device Select bits (b6, b5, b4). They are matched to the chip enable signals applied on pins E2, E1, E0. Thus up to 8 x 16K memories can be connected on the same bus giving a memory capacity total of 128 Kbits. After a START condition any memory on the bus will identify the device code and compare the 3 bits to its chip enable inputs E2, E1, E0. The 8th bit sent is the read or write bit (RW). This bit is set to '1' for read and '0' for write operations. If a match is found, the corresponding memory will acknowledge the identification on the SDA bus during the 9th bit time. If the memory does not match the Device Select code, it will self-deselect from the bus and go into standby mode. Write Operations Following a START condition the master sends a Device Select code with the RW bit set to '0'. The memory acknowledges it and waits for a byte address, which provides access to the memory area. After receipt of the byte address, the memory again responds with an acknowledge and waits for the data byte. Writing in the Memory may be inhibited if input pin WC is taken high. Any write command with WC=1 (during a period of time from the START condition until the Acknowledge of the last Data byte) will not modify the memory content and will NOT be acknowledged on data bytes, as shown in Figure 9. Byte Write. In the Byte Write mode, after the Device Select code and the address, the master sends one data byte. If the addressed location is write protected by the WC pin, the memory send a NoACK and the location is not modified. If the WC pin is tied to 0, after the data byte the memory sends an ACK. The master terminates the transfer by generating a STOP condition. Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus VCC 20 Maximum RP value (k) 16 RL 12 8 4 0 10 100 CBUS (pF) AI01665 RL SDA MASTER fc = 100kHz fc = 400kHz SCL CBUS CBUS 1000 4/16 M24164 Table 5. Input Parameters (1) (TA = 25C, f = 400 kHz ) Symbol CIN CIN tLP Parameter Input Capacitance (SDA) Input Capacitance (other pins) Low-pass filter input time constant (SDA and SCL) 200 Test Condition Min Max 8 6 500 Unit pF pF ns Note: 1. Sampled only, not 100% tested. Table 6. DC Characteristics (TA = 0 to 70C or -40 to 85C; VCC = 4.5V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V) Symbol ILI ILO Parameter Input Leakage Current (SCL, SDA) Output Leakage Current Supply Current ICC Supply Current (-W series) Supply Current (-R series) ICC1 ICC2 ICC3 VIL VIH VIL VIH VOL Supply Current, Standby Supply Current, Standby (-W series) Supply Current, Standby (-R series) Input Low Voltage (SCL, SDA, E2, E1, E0) Input High Voltage (SCL, SDA, E2, E1, E0) Input Low Voltage (WC) Input High Voltage (WC) Output Low Voltage Output Low Voltage (-W series) Output Low Voltage (-R series) IOL = 3mA, VCC = 5V IOL = 2.1mA, VCC = 2.5V IOL = 0.15mA, VCC = 1.8V Test Condition 0V VIN VCC 0V VOUT VCC SDA in Hi-Z VCC = 5V, fC = 400kHz (Rise/Fall time < 30ns) VCC = 2.5V, fC = 400kHz (Rise/Fall time < 30ns) VCC = 1.8V, fC = 100kHz (Rise/Fall time < 30ns) VIN = VSS or VCC, VCC = 5V VIN = VSS or VCC, VCC = 2.5V VIN = VSS or VCC, VCC = 1.8V -0.3 0.7 VCC -0.3 VCC - 0.5 Min Max 2 2 2 1 0.8 20 1 0.1 0.3 VCC VCC + 1 0.5 VCC + 1 0.4 0.4 0.2 Unit A A mA mA mA A A A V V V V V V V 5/16 M24164 Table 7. AC Characteristics M24164 Symbol Alt Parameter VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V TA = 0 to 70C TA = 0 to 70C TA = 0 to 70C TA = -40 to 85C TA = -40 to 85C TA = -40 to 85C Min tCH1CH2 tCL1CL2 tDH1DH2 (1) tDL1DL2 (1) Unit Max 300 300 Min Max 300 300 Min Max 1000 300 ns ns ns ns ns ns ns s s ns ns s 3500 ns ns 100 10 kHz ms tR tF tR tF tSU:STA tHIGH tHD:STA tHD:DAT tLOW tSU:DAT tSU:STO tBUF tAA tDH fSCL tWR Clock Rise Time Clock Fall Time SDA Rise Time SDA Fall Time Clock High to Input Transition Clock Pulse Width High Input Low to Clock Low (START) Clock Low to Input Transition Clock Pulse Width Low Input Transition to Clock Transition Clock High to Input High (STOP) Input High to Input Low (Bus Free) Clock Low to Next Data Out Valid Data Out Hold Time Clock Frequency Write Time 20 20 600 600 600 0 1.3 100 600 1.3 200 200 300 300 20 20 600 600 600 0 1.3 100 600 1.3 300 300 20 20 4700 4000 4000 0 4.7 250 4000 4.7 1000 300 tCHDX (2) tCHCL tDLCL tCLDX tCLCH tDXCX tCHDH tDHDL tCLQV (3) tCLQX fC tW 900 200 200 900 200 200 400 5 400 10 Notes: 1. Sampled only, not 100% tested. 2. For a reSTART condition, or following a write cycle. 3. The minimum value delays the falling/rising edge of SDA away form SCL = 1 in order to avoid unwanted START and/or STOP condition. Table 8. AC Measurement Conditions Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 50ns 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Figure 4. AC Testing Input Output Waveforms 0.8VCC 0.7VCC 0.3VCC AI00825 0.2VCC 6/16 M24164 Figure 5. AC Waveforms tCHCL SCL tDLCL SDA IN tCHDX START CONDITION tCLDX SDA INPUT SDA CHANGE tCLCH tDXCX tCHDH tDHDL STOP & BUS FREE SCL tCLQV SDA OUT DATA VALID tCLQX DATA OUTPUT SCL tW SDA IN tCHDH STOP CONDITION WRITE CYCLE tCHDX START CONDITION AI00795B Page Write. The Page Write mode allows up to 16 bytes to be written in a single write cycle, provided that they are all located in the same 'row' in the memory: that is the most significant memory address bits are the same. The master sends from one up to 16 bytes of data, each of which is acknowledged by the memory if the WC pin is low. If the WC pin is high, each data byte is followed by a NoACK and the location will not be modified. After each byte is transferred, the internal byte address counter (4 least significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition. Care must be taken to avoid address counter 'roll-over' which could result in data being overwritten. Note that, for any byte or page write mode, the generation by the master of the STOP condition starts the internal memory program cycle. All inputs are disabled until the completion of this cycle and the memory will not respond to any request. 7/16 M24164 Figure 6. I2C Bus Protocol SCL SDA START CONDITION SDA INPUT SDA CHANGE STOP CONDITION SCL 1 2 3 7 8 9 SDA MSB ACK START CONDITION SCL 1 2 3 7 8 9 SDA MSB ACK STOP CONDITION AI00792 Minimizing System Delays by Polling On ACK. During the internal write cycle, the memory disconnects itself from the bus in order to copy the data from the internal latches to the memory cells. The maximum value of the write time (tW) is given in the AC Characteristics table, since the typical time is shorter, the time seen by the system may be reduced by an ACK polling sequence issued by the master. The sequence is: - Initial condition: a Write is in progress (see Figure 7). - Step 1: the master issues a START condition followed by a Device Select byte (1st byte of the new instruction). - Step 2: if the memory is busy with the internal write cycle, NoACK will be returned and the master goes back to Step 1. If the memory has terminated the internal write cycle, it will respond with an ACK, indicating that the memory is ready to receive the second part of the incoming instruction (the first byte of this instruction was already sent during Step 1). 8/16 M24164 Figure 7. Write Cycle Polling using ACK WRITE Cycle in Progress START Condition DEVICE SELECT with RW = 0 NO First byte of instruction with RW = 0 already decoded by M24xxx ACK Returned YES NO Next Operation is Addressing the Memory YES ReSTART Send Byte Address STOP Proceed WRITE Operation Proceed Random Address READ Operation AI01847 9/16 M24164 Figure 8. Write Modes Sequence ACK BYTE WRITE DEV SEL ACK DATA IN ACK BYTE ADDR R/W ACK ACK START ACK DATA IN 1 DATA IN 2 PAGE WRITE DEV SEL BYTE ADDR R/W START ACK DATA IN N ACK STOP STOP AI01941 Read Operations Read operations are independent from the state of the WC input pin. On delivery, the memory contents is set at all "1's" (or FFh). Current Address Read. The memory has an internal byte address counter. Each time a byte is read, this counter is incremented. For the Current Address Read mode, following a START condition, the master sends a Device Select code with the RW bit set to '1'. The memory acknowledges this and outputs the byte addressed by the internal byte address counter. This counter is then incremented. The master have to NOT acknowledge the byte output and terminates the transfer with a STOP condition. Random Address Read. A dummy write is performed to load the memory address into the address counter, see Figure 10. This is followed by another START condition from the master and the Device Select code is repeated with the RW bit set to '1'. The memory acknowledges this and outputs the byte addressed. The master have to NOT acknowledge the byte output and terminates the transfer with a STOP condition. Sequential Read. This mode can be initiated with either a Current Address Read or a Random Address Read. However, in this case the master DOES acknowledge the data byte output and the memory continues to output the next byte in sequence. To terminate the stream of bytes, the master must NOT acknowledge the last byte output and MUST generate a STOP condition. The output data is from consecutive byte addresses, with the internal byte address counter automatically incremented after each byte output. After a count of the last memory address, the address counter will 'rollover' and the memory will continue to output data. Acknowledge in Read Mode. In all read modes the memory wait for an acknowledge during the 9th bit time. If the master does not pull the SDA line low during this time, the memory terminate the data transfer and switches to a standby state. 10/16 M24164 Figure 9. Write Modes Sequence with Write Control = 1 WC ACK BYTE WRITE DEV SEL ACK NO ACK DATA IN BYTE ADDR R/W START WC ACK PAGE WRITE DEV SEL ACK NO ACK DATA IN 1 NO ACK BYTE ADDR R/W WC (cont'd) NO ACK PAGE WRITE (cont'd) NO ACK START DATA IN N STOP STOP DATA IN 2 AI02038 11/16 M24164 Figure 10. Read Modes Sequence ACK CURRENT ADDRESS READ DEV SEL NO ACK DATA OUT R/W START ACK RANDOM ADDRESS READ DEV SEL * ACK DEV SEL * STOP ACK NO ACK DATA OUT BYTE ADDR START R/W START R/W ACK SEQUENTIAL CURRENT READ DEV SEL ACK ACK NO ACK DATA OUT 1 R/W DATA OUT N START ACK SEQUENTIAL RANDOM READ DEV SEL * ACK DEV SEL * ACK ACK BYTE ADDR DATA OUT 1 R/W START R/W ACK NO ACK DATA OUT N STOP START AI01942 Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical. 12/16 STOP STOP M24164 ORDERING INFORMATION SCHEME Example: M24164 - R MN 1 T Density 164 16 Kbit Operating Voltage blank W R 4.5V to 5.5V 2.5V to 5.5V 1.8V to 5.5V Package BN PSDIP8 0.25mm Frame MN SO8 150mil Width Temperature Range 1 (1) 0 to 70 C 6 3 (2) Option T Tape & Reel Packing -40 to 85 C -40 to 125 C Notes: 1. Temperature range on request only. 2. Produced with High Reliability Certified Flow (HRCF), in VCC range 4.5V to 5.5V at 100kHz only. Devices are shipped from the factory with the memory content set at all "1's" (FFh). For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 13/16 M24164 PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame Symb Typ A A1 A2 B B1 C D E E1 e1 eA eB L N 2.54 7.62 mm Min 3.90 0.49 3.30 0.36 1.15 0.20 9.20 - 6.00 - 7.80 - 3.00 8 Max 5.90 - 5.30 0.56 1.65 0.36 9.90 - 6.70 - - 10.00 3.80 0.100 0.300 Typ inches Min 0.154 0.019 0.130 0.014 0.045 0.008 0.362 - 0.236 - 0.307 - 0.118 8 Max 0.232 - 0.209 0.022 0.065 0.014 0.390 - 0.264 - - 0.394 0.150 A2 A1 B B1 D N A L eA eB C e1 E1 1 E PSDIP-a Drawing is not to scale. 14/16 M24164 SO8 - 8 lead Plastic Small Outline, 150 mils body width mm Typ A A1 B C D E e H h L N CP 1.27 Min 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ inches Min 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8 Symb A2 B e D A C CP N E 1 H A1 L SO-b Drawing is not to scale. 15/16 M24164 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - All Rights Reserved Purchase of I2C Components by STMicroelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com 16/16 |
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